Engineers create the first AI model specialized in chip design languages

Researchers at the NYU Tandon School of Engineering created the first specialized artificial intelligence model, Verigen. This was successfully trained to generate Verilog code, a programming language that explains how the circuitry on the chip works.

This study has just won an ACM transaction on design automation for the Electronic Systems 2024 Best Paper Award, and has affirmed it as a major advance in automating the creation of hardware description languages ​​that required traditional deep technical expertise.

“We are a great place to go,” said Siddharth Garg, who sits in the Department of Electrical Engineering (ECE) at NYU Tandon and works at NYU Wireless and the NYU Center of NYU Center (CCCS). “These models tend to work well in programming languages ​​that are often expressed in Github, such as C and Python, but they tend to be worse in languages ​​with poorly expressed expressions like Verilog.”

Ramesh Karri and Brendan Dolan-Gavitt, students, postdoctoral researchers and faculty members, along with Garg, a team at NYU Tandon Ph.D., addressed this challenge by creating and distributing the largest AI training dataset of Verilog code ever constructed. They scrutinised Github to collect about 50,000 Verilog files from public repositories and supplemented this with content from 70 Verilog textbooks. This data collection process required careful filtering and duplication weighting to create a high-quality training corpus.

For the most powerful model, researchers have since tweaked Salesforce’s open source CodeGen-16B language model, which contains 16 billion parameters and was originally pre-trained in both natural and programming code.

The calculation requirements were substantial. Training required a complete training process, with three NVIDIA A100 GPUs running in parallel, consumed 30 GB of memory on model parameters alone and required around 250 GB of GPU memory.

This fine-tuned model works impressively in testing, surpassing commercial cutting edge models, several orders of magnitude smaller and is completely open source. In the evaluation, the fine-tuned CodeGen-16B achieved a 41.9% percentage of functionally correct code, versus 35.4% of the commercial code Davinci-002 model.

“We’ve shown that by tweaking the model for a specific task you care about, you can reduce the size of your model by orders of magnitude,” Garg said, highlighting how that approach improves both accuracy and efficiency. Because of its small size, the model can run on a standard laptop rather than requiring special hardware.

The team evaluated Verigen’s capabilities across increasingly complex hardware design tasks, from basic digital components to sophisticated finite state machines. Although not yet complete, especially for the most complex challenges, Verigen has shown significant improvements over the generic model, particularly when generating syntactically correct code.

The importance of this work is recognized in this field, with subsequent research by Nvidia in 2025 recognizing Verigen as one of the earliest and most important benchmarks of LLM-based Verilog Generation, helping to establish the foundation for rapid advancements in AI-Assisted Hardware Design.

The open source nature of the project has already sparked great interest in this area. Verigen was the first model of the team presented in the ACM paper, but later developed an improved family of models called “Cl Verilog” that performed even better.

These new models are being offered to hardware companies, including Qualcomm and NXP, to evaluate potential commercial applications. The work is based on previous NYU Tandon efforts, including the Dave (automatically Verilog from English) project in 2020, and advances the field by creating more comprehensive solutions through extensive tweaks of the language model.

Verigen complements other AI-assisted-chip design initiatives from NYU Tandon, which aims to democratize hardware. Their Chip Chat Project created the first functional microchip designed through natural language conversation with GPT-4. Supported by the National Science Foundation (NSF) research training program, Chips4all trains a diverse range of STEM graduate students in chip design. Funded through experiential learning for NSF’s emerging and new technology initiatives, the fundamentals teach chip design to non-STEM professionals.