Gallium Nitride Transistors Increase Chip Speed ​​and Efficiency in New 3D Designs

The advanced semiconductor material, gallium nitride, can be key to the power electronics needed for next-generation high-speed communication systems and cutting-edge data centers.

Unfortunately, the high cost of gallium nitride (GAN) and the specialization required to incorporate this semiconductor material into traditional electronic devices limit its use in commercial applications.

Currently, researchers at MIT and elsewhere have developed a new manufacturing process that integrates high-performance GAN transistors into standard silicon CMOS chips, low cost, scalable, and in a way that is compatible with existing semiconductor foundries.

Those methods involve building many small transistors on the surface of the GAN chip, cutting out individual transistors, then glueing as many transistors as needed to the silicon chip using a cold process that preserves the functionality of both materials.

The cost is minimized as only a small amount of GAN material is added to the CHIP, but the resulting device can significantly increase performance from compact, high-speed transistors. Furthermore, by separating the GAN circuit into discrete transistors that can be spread over a silicon chip, new technology can reduce the temperature of the entire system.

The researchers used this process to fabricate power amplifiers, a key component of mobile phones that achieves higher signal strength and efficiency than devices with silicon transistors. Smartphones can improve call quality, increase wireless bandwidth, increase connectivity and extend battery life.

The method meets standard procedures, and as with future technology, it can improve the electronics that exist today. In the future, new integration schemes can even enable quantum applications, as Gan performs better than silicon at cryogenic temperatures, which are essential for many types of quantum computing.

“It’s easy to adopt this technology if we can reduce costs, improve scalability, and at the same time improve the performance of our electronic devices.

“These hybrid chips can revolutionize many commercial markets,” said Pradyot Yadav, a graduate student at MIT and lead author of a paper on the methodology. This paper was presented at the RTU2C session at the Radio Frequency Integrated Circuit Symposium (RFIC 2025) held in San Francisco, California from June 15-17, 2025.

Replace the transistor

Gallium nitride is the second most widely used semiconductor in the world right after silicon, and its unique properties make it ideal for applications such as lighting, radar systems, and power electronics.

This material has been around for decades, and to access maximum performance, it is important that a chip made of GAN connects to a digital chip made of silicon, also known as a CMOS chip. To enable this, some integration methods connect the GAN transistor to the CMOS chip by soldering the connection, which limits how small the GAN transistor is. The smaller the transistor, the more frequently you can work on it.

Other methods integrate the entire gallium nitride wafer on top of the silicon wafer, but using so many materials is very costly, especially since Gan is only needed with a few small transistors. The rest of the Gan Wafer material will be wasted.

“We wanted to combine the power of a digital chip made from silicon to the functionality of a GAN, but we achieved this by adding a gallium nitride transistor to the right on top of the silicon chip without compromising on either bandwidth cost,” explains Yadav.

The new chip is the result of a multi-stage process.

First, a solidly packed collection of Minuscule transistors is manufactured throughout the surface of the Gan Wafer. Using very fine laser technology, cut each one out to only the size of the transistor. This is 240 x 410 microns and forms what is called a dillet. (Microlon is one millionth of a meter.)

Each transistor is fabricated with small copper columns at the top and is used to directly bond to copper columns on the surface of standard silicon CMOS chips. Copper to copper bonding can be made at temperatures below 400 degrees Celsius.

Current GAN integration technologies require bonds that utilize gold, an expensive material that requires much higher temperatures and stronger bonding forces than copper. Gold can contaminate the tools used in most semiconductor foundries, so special facilities are usually required.

“We wanted a process that would win against all those involved with gold, low-cost, low-force, low-force. At the same time, it has improved conductivity,” Yadav says.

New tools

To enable the integration process, we have created a new specialized tool that allows us to carefully integrate very small GAN ​​transistors with silicon chips. This tool uses a vacuum to hold the dillet as it moves over the silicon chip and zeroes at the copper bond interface with nanometer accuracy.

They monitor the interface using an advanced microscope, then apply heat and pressure to couple the GAN transistor to the chip when the deallet is in the correct position.

“For each step of the process, I had to know how to do the necessary techniques, learn it, and find a new collaborator to integrate it into my platform.

Once researchers completed the manufacturing process, they demonstrated this by developing a power amplifier, a radio frequency circuit that enhances wireless signals.

Their devices achieved higher bandwidth and better gain than devices made with traditional silicon transistors. Each compact chip has an area of ​​less than half square millimeters.

Additionally, the silicon chips used in the demo are based on Intel 16 22nm Finfet cutting-edge metallization and passive options, allowing for the incorporation of components commonly used in silicon circuits, such as neutralization capacitors. This significantly improves the gain of the amplifier, bringing us a step closer to enabling next-generation wireless technology.

“To address the slowdown of Moore’s law in transistor scaling, non-uniform integration has emerged as a promising solution for continuous system scaling, reduced form factors, improved power efficiency and optimisation of costs.

“In particular, in wireless technology, tight integration of composite semiconductors with silicon-based wafers is critical to achieving memory integrated systems for front-end integrated circuits, baseband processors, accelerators, and next-generation antenna-to-AI platforms.

“This work will make important advances by demonstrating multiple GAN chips to 3D integration with silicon CMOS and 6D, pushing the boundaries of current technical capabilities,” said Atom Watanabe, an IBM research scientist who is not involved in the paper.

This story has been republished courtesy of MIT News (web.mit.edu/newsoffice/), a popular site that covers news about MIT research, innovation and education.