Sorting tasks are ubiquitous in many applications. CPU/GPU or ASIC-based sorting systems employ large comparison units. Performance is limited by the bandwidth between the CMOS device and the memory and the comparison unit. Sorting Nair Memory relieves bandwidth bottlenecks. Sort-in-Memory based on Memristor-Aided Logic utilizes Memristors, but relies on comparison operations. Comparative MSIM using the TNS/CA-TNS strategy solves three bottlenecks. Credit: Yu et al.
Organizing data in a specific order, also known as sorting, is a central computing operation performed by a wide range of systems. Traditional hardware systems rely on individual components to store and sort data, limiting speed and energy efficiency.
Researchers at Peking University recently relied on Memrista to develop a new reconfigurable sort-in memory system that relies on stored data. Their proposed system, published in Nature Electronics and outlined in a paper led by Professor Yuchao Yang, has been found to store and sort data both quickly and energy efficient.
“The original idea is that operations such as multiplication and convolution of a matrix are widely implemented in CIM (computing-in-memory) systems, but due to their unique computational properties, sorting has long been considered the ‘hard nut’ of memory technology,” he told the authors who corresponded to TheTechXPlore.
“First, traditional sorting hardware involves extensive comparisons and selection logic, conditional branching, or swap operations. This features linear operations that CIM (Memory-in Memory) is superior to fundamentally different irregular control flows. Second, sorting over a large amount of data often leads to highly dynamic memory access patterns that compete with the structured memory access design of CIM.
It has been found that most algorithms of sorting developed so far also exhibit strong data dependencies. This essentially means that the operations they perform depend on the outcome of previous operations. This makes high-end operations difficult and reduces the benefits of CIM systems in tasks that perform multiple operations simultaneously.
“The reason it remains a sort dependency remains an unsolved challenge in CIM development, lies in the “unstructured” and “control-intensive” computationality, which is essentially inconsistent with current CIM design principles, centered around linear acceleration of memory,” explained Tao.
“Overcoming the implementation of sorts in CIM not only solves important engineering challenges, but also represents the key steps to making CIM a generic intelligent computing technology. The main goal of our research is to realize the main goal of “in-situ” and develop sort-in memory technology compatible with cutting-edge memory techniques.”
As part of this recent research, the new reconfigurable sort-in memory system developed by Tao and his colleagues consists of one translistol one resistor (1T1R) memoryster array and peripheral circuits. The peripheral circuits are divided into three different modules called numeric processors, numeric selectors, and state controllers.
“These components can access 1T1R Memristor arrays and reconfigure to support the variable data types in the literature, which can meet the needs of real sorting applications, including unsigned, two completions, or fixed points or floating point numbers of sine and magnitude,” explained TAO.
“Their unique advantages/characters include support for three different parallelism enhancement methodologies, a multi-bank strategy for higher number-level parallelism, a bit-slicing strategy for higher bit-level parallelism, and a multi-level strategy for higher in-device parallelism.”
This work, enabled in Memristor Devices, develops 1T1R arrays for numeric reading (DR), TNS/CA-TNS technology for non-comparative SIMs, and end-to-end MSIM systems for practical demonstrations. Credit: Yu et al.
In the first test, the new sort-in memory scheme devised by this team’s team produced very promising results as it requires significantly less energy than the approach introduced in sort data previously introduced. Furthermore, the scheme is highly versatile and adaptable, integrated with a variety of other systems and coordinated to meet the requirements of a particular real-world problem.
“The scheme enables three parallel processing enhancement strategies, including multibank, bitslice and multi-level conductance, making it compatible with state-of-the-art memory for matrix vector multiplication,” says Tao. “Sorting algorithms play an important role in data processing by rapidly ranking large volumes of candidate data and identifying the most relevant items for further analysis.
“In scenarios such as large-scale language model training, robot path planning, and augmented learning searches, both rapid evaluation and ranking of multiple decisions or actions are essential and very time-consuming. However, sort operations include nonlinear operations and irregular data access patterns, and currently lack the common, efficient hardware appmitivities for sorting.”
Currently available memory (PIM) architectures are known to have major limitations, such as the inability to efficiently sort large amounts of data. This has so far been limited to scenarios with limited deployments.
A new approach developed by Tao and his colleagues may help overcome the shortcomings of these PIM architectures, which increases the efficiency of storing and sorting the system as they tackle a wider range of tasks. In the future, it could be deployed in healthcare facilities and manufacturing sites. It may also be used to efficiently organize scientific databases and optimize smart transport solutions.
“We are currently working on improving the sorting system of memory systems and integrating it into cutting-edge computing systems for AI or other emerging scenarios,” Tao added. “Our ultimate goal is to deploy this technology to more common hardware systems, where sorting becomes a computational bottleneck.”
Written for you by author Ingrid Fadelli, edited by Gaby Clark and fact-checked and reviewed by Andrew Zinin. This article is the result of the work of a careful human being. We will rely on readers like you to keep independent scientific journalism alive. If this report is important, consider giving (especially every month). You will get an ad-free account as a thank you.
Details: A fast and reconfigurable sort-in memory system based on Lianfeng Yu et al, Memristors, Nature Electronics (2025). doi: 10.1038/s41928-025-01405-2.
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Citation: New Reconfigurable Memristor-based System Retrieved from https://techxplore.com/news/2025-07-Reconfigurable-Memristor-Enables-memory.htmllidmllied, retrieved from 23rd July 2025
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